http://forum.6502.org/viewtopic.php?t=1671 - discussion of a VHDL version of 6502 processor.
http://forum.6502.org/viewtopic.php?t=1824 - The idea with 65Org16 was that it was the least-effort method of getting a lot of memory easily available on a 6502-like CPU. It wasn't meant to be fast or to have a lot of extra capabilities or denser code.
Well, I finally did some hacking this afternoon, using Arlet's core as a basis, and it does seem to be relatively straightforward to cook up a version of 6502 with 16-bit registers and a 32-bit address space. The way to look at this is as a 6502 where a byte has 16 bits. There is no particular support for an 8-bit data type or peripheral - you roll your own.
Question is: who's genuinely interested in a 6502-like CPU, implemented on FPGA, which can address up to 4 gigawords of 16-bit wide memory?
http://forum.6502.org/viewtopic.php?t=1673 -
10 6502 Cores are compared as far as the resources consumed in an XC2S200. No speed or performance comparisons are made here, that may be for another thread!
The Spartan 2 family was chosen for their 5v input compatibility.
Xilinx ISE 10.1 is used although very "buggy" (read:not impossible to work with), because all future versions of ISE are exclusive of the Spartan 2 family.
I chose the XC2S200 208-pin QFP after trying a smaller XC2S100, which did not have enough resources to fit any of the cores presented here.
http://opencores.org/project,t65